This invention relates to a delay circuit for continuously varying a delay time by an electric signal applied to a control terminal and also to an ultrasonic diagnosis apparatus capable of dynamic focusing by using this delay circuit in the phasing circuit.
The ultrasonic diagnosis apparatus sends and receives ultrasonic waves to and from a human body under medical examination through a probe, and obtains information about the inside of the examined body from the reflected wave signal from the inside of the examined body. To obtain images with high resolution of any places at different depths of the inside of the examined body, when receiving the reflected waves from inside the body, dynamic focusing is performed which dynamically varies the focus of the received waves with passage of time. In dynamic focusing, the reflected waves are received by the individual oscillator elements of a probe comprising a plurality of narrow, strip-shaped oscillator elements or a probe comprising concentric, ring-shaped oscillator elements, and the received wave signals are brought to focus by delaying those signals in suitable degrees by using delay lines and adding those signals. This circuit is generally called a phasing circuit. The focal positions of the received waves are determined by delay times of the delay lines. Therefore, dynamic focusing is achieved by dynamically varying the delay times to be given to a plurality of received wave signals according to the depths in the examined body at which the ultrasonic waves are reflected back.
Conventionally, the above-mentioned delay times are varied by providing the delay lines with taps at suitable intervals and selectively switching over from one tap to another with an electronic switch. In this case, when the above-mentioned electronic switch is operated, noise sometimes occurs and enters the received wave signals through the delay lines, so that wrong signals occasionally appear in diagnostic information. To remove this phenomenon, it is only necessary to use a type of switch less liable to produce noise as the electronic switch mentioned above. However, this method has a problem of wastefulness that such an electronic switch is expensive and if many such switches are mounted to correspond to the number of taps of the delay lines, production cost rises.
So, a delay circuit has emerged which uses variable delay elements, each comprising a variable capacity diode and a resistor.
Before proceeding to description of this variable delay element, the principle of the RC delay element will be described with reference to FIG. 1.
In FIG. 1, reference numeral 21 denotes an ideal operational amplifier with a gain of 1, and 22 denotes an ideal operational amplifier with a gain of -1. As illustrated, the ideal operational amplifier 21 is connected in series with a resistor, and the ideal operational amplifier 22 is connected in series with a capacitor, and these two series circuits are connected in parallel.
The transfer function of this circuit network is expressed by the following expression (1). EQU E.sub.out /E.sub.in =sCR/(1+sCR) (1)
where s=j.omega. and j.sup.2 =-1
From the expression (1), the equation to find the delay time T is given as follows. EQU T=2RC/(1+.omega..sup.2 R.sup.2 C.sup.2) (2)
To be more specific, the delay time when the angular frequency .omega. is sufficiently smaller than 1/CR, the delay time is 2RC, and by varying the resistance value or the capacity value, the delay time can be varied. In practice, by using a variable capacity diode the capacitance of which is varied by an electric signal, the delay time can be varied.
As means for effecting variable delay mentioned above, a so-called variable delay circuit which can control the delay time by an electric signal instead of the above-mentioned delay line with taps has been proposed in Japanese Utility Model Application Laid Open No. 63-129863. As shown in FIG. 3, this variable delay circuit 1 receives an input signal Ein supplied from the base of the transistor Tr, and outputs, respectively from the emitter and collector of the transistor Tr, a positive phase signal and a negative phase signal with respect to the input signal Ein, which signals have substantially equal amplitudes and a phase difference of 180.degree. between them. The positive phase signal is input to one end of a series circuit of two variable capacity diodes VC.sub.1 and VC.sub.2 in series with their cathodes tied together, the capacitance of the two variable capacity diodes VC.sub.1 and VC.sub.2 is varied by the magnitude of the reverse voltage Ec, while the negative phase signal from the above-mentioned collector is input to one end of a resistor R. The other end of the series circuit of the above-mentioned variable diodes VC.sub.1 and VC.sub.2 and the other end of the above-mentioned resistor R are connected together to provide an output signal Eout. In this circuit configuration, the delay time used to be varied by a change in the reverse voltage Ec applied to the above-mentioned variable capacity diodes.
In FIG. 3, a symbol Rin denotes a resistor to give an electric potential to the base of the transistor Tr, and a symbol Rb denotes a resistor to prevent oscillation. Meanwhile, the load resistors RV- and RV+ in the emitter and collector circuits of the transistor Tr have substantially equal resistance values to ensure that the amplitude of the signal voltage at the emitter is equal to the amplitude of the signal voltage at the collector. Therefore, the above-mentioned transistor Tr works as a phase splitter. With regard to the output signals which differ 180.degree. in phase in the transistor Tr, one signal is sent through the variable capacity diodes VC.sub.1 and VC.sub.2 to which the reverse voltage Ec is applied through a resistor r, and the other signal is sent through the resistor R, and the two signals are added together and output as an output signal Eout.
Either one of the above-mentioned variable capacity diodes VC.sub.1 and VC.sub.2 may be a fixed capacitor. In the variable delay circuit shown in the above-mentioned published utility model application, the circuits shown in FIG. 3 connected in a multi-stage cascade connection are used.
In the variable delay circuit 1 shown in FIG. 3, if the input voltage at the input terminal is denoted by Ein, the output voltage at the output terminal by Eout, the capacitance of the variable capacity diodes VC.sub.1 and VC.sub.2 by C and the constant by s, the transfer function of this circuit network is expressed as follows. ##EQU1## where s =j.omega. (j : complex number, .omega.: angular frequency of signal)
The above expression (3) corresponds to a first-order allpass transfer function. In this case, if the phase transition amount is denoted by .beta. (.omega.), the phase transition amount can be given by EQU .beta.(.omega.)=-2 tan.sup.-1 .omega.RC (4)
If the delay time Tgd is obtained from the expression (3), Tgd is given as follows. ##EQU2##
In this expressed (5), when (.omega.RC).sup.2 &lt;&lt;1, the delay time Tgd is the value of 2RC regardless of the magnitude of .omega., that is, a value proportional to the resistance value of the resistor R or the capacitance C of the variable capacity diodes VC.sub.1 and VC.sub.2. Therefore, assuming that the resistance R is constant, by varying the capacitance C of the variable capacity diodes VC.sub.1 and VC.sub.2, the delay time Tgd can be controlled continuously.
As another example of prior art, there has been proposed in JP-A-62-137043 that a delay circuit which is controlled by an electric signal. The delay circuit in this patent application publication, as shown in FIG. 2, is a circuit made up of a combination of two transistors TR.sub.1 and TR.sub.2, a resistor R, and a variable capacity diode VC, and this delay circuit controls the delay time by varying the capacitance of the above-mentioned variable capacity diode VC by an electric signal from a control terminal 2 to thereby effect dynamic focusing.
In yet another example, as shown in FIG. 6, by transposing the positions where the resistor R and the variable capacity diode VC are connected in FIG. 2, and adjusting the resistor R73, the attenuation of signal can be corrected.
A similar circuit is carried in Arthur B. Williams "ELECTRONIC FILTER DESIGN HANDBOOK" McGraw-Hill 1981.
In FIG. 6, IN denotes a signal input terminal, OUT denotes a signal output terminal, CNT denotes a capacity control signal (delay time control signal) input terminal, V.sub.CC denotes a power source, C71 and C72 denotes capacitors, R71 to R77 denote resistors, and TR2 and TR3 denote transistors.
In the delay circuit 1 mentioned earlier, however, since there is a theoretical limit to the frequency characteristics of the delay time, a large delay amount cannot be set for each section thereof. So, it is possible to form a circuit having the above-mentioned delay circuits 1 connected in multiple stages to obtain a necessary delay amount, but this gives rise to a problem that current consumption increases which is uneconomical. In addition, another problem arises that the high frequency characteristics deteriorate due to the Miller effect in the first transistor TR.sub.1 for providing positive and negative phase signals with respect to an input signal to be delayed.
FIG. 4 shows an example of calculations of the frequency-gain characteristics of the output signal when a fixed capacity C is used in place of the variable capacity diodes VC.sub.1 and VC.sub.2 in FIG. 4, and the circuit constants are given as shown below, and FIG. 5 shows an example of calculations of the frequency-delay time characteristics.
______________________________________ Circuit constants ______________________________________ Power source +Vcc +12 V Power source -Vcc -6 V Resistor Rin 10 k.OMEGA. Resistor Rb 108 .OMEGA. Resistor RV+ 1 k.OMEGA. Resistor RV- 1 k.OMEGA. Resistor R 250 .OMEGA. Capacitor C 20 pF ______________________________________
Incidentally, in FIG. 3, since the resistor r has a sufficiently large value, the terminal of the resistor r was regarded as open in the calculations. As is obvious from FIG. 5, when the frequency exceeds a certain value, the delay time decreases as the frequency increases. For example, it will be understood that the frequency at which the delay time substantially constant over a range of frequencies decreases about 10% is about 7.8 MHz.
In the variable delay circuit 1 shown in FIG. 3, however, the delay time suddenly decreases when the frequency becomes higher than a certain value as shown in FIG. 5. In the frequency-delay time characteristics shown in FIG. 5, to raise the upper limit of the frequencies that can maintain the delay time at a substantially constant length, it is only necessary to use a small capacitance C in the expression (5) mentioned above to set a reduced delay time for every one stage, and connect variable delay circuits 1, shown in FIG. 3, in a multi-stage cascade connection to obtain a required length of delay time. However, in such a circuit configuration, the number of parts used increases and the circuit becomes large, resulting in a large current consumption and a high cost. As a solution to this problem, to decrease the size of the above-mentioned variable delay circuit and reduce cost, it is desirable that the delay time for every one stage of circuit does not decrease up to a high frequency range.
An ultrasonic diagnosis apparatus using a conventional delay circuit, such as this, has a received wave phasing circuit included, and this received wave phasing circuit comprises a circuit which performs what they call focusing of received waves by giving a predetermined delay to the individual outputs from the respective oscillator elements in the ultrasonic probe and adding up the output signals.
FIG. 7 shows an example of a concrete circuit configuration. In FIG. 7, the received wave phasing circuit comprises delay circuit sections 43 each including a first fixed delay circuit 413, a second fixed delay circuit 414, and an aperture control circuit 416, and a third fixed delay circuit 42. Each delay circuit section 43 accepts received wave signals from four channels out of all channels of the oscillator elements of an ultrasonic probe, not shown, and the received wave signals of the four channels are each given predetermined delays by the first fixed delay circuit 413 and the second fixed delay circuit 414, and the delayed outputs are added together by the second fixed delay circuit 414.
The aperture control circuit 416 comprises circuits for controlling the variable aperture for improving the ultrasonic beam characteristics by varying the aperture according to the reception time, and more specifically, the aperture control circuit 416 is formed by a switch circuit which allows a signal to pass or cut it off.
Signals from the delay circuit 43 are sent to the third fixed delay circuit 42.
The received wave phasing circuit 4 has a plurality of delay circuit sections 43. For example, if the received wave phasing circuit is a 64-channel unit, the phasing circuit includes 16 delay circuit sections 43, and if the received wave phasing circuit is a 128-channel unit, the phasing circuit includes 32 delay circuit sections 43.
Signals from the delay circuit section 43 are sent to the third fixed delay circuit 42, and are each given predetermined delay amounts, and are added together. The delay circuit section 43 chiefly controls focusing while the third fixed delay circuit 42 chiefly controls the scanning direction of the ultrasonic beam (deflection of the ultrasonic beam).
In the received wave shaping circuit thus constructed, when dynamic focusing of the received waves is performed, it is only necessary to vary the delay times for outputs from the individual oscillator elements while receiving the waves.